• Aldec Active-HDL 8.1

    FPGA Design "Made easy" Active-HDL™ is a Windows® based integrated FPGA Design and Simulation solution. Active-HDL includes a full HDL graphical design tool suite and RTL/gate-level mixed-language Simulator. The design flow manager evokes 80 plus EDA and FPGA tools, during design, simulation, synt.....
    Language : english Authorization: Retail Freshtime:2008-10-09 Size: 818MB
  • Synopsys Synplify FPGA 9.61

    Synplicity’s Synplify Premier software is the ultimate FPGA timing closure and debug solution. It builds upon Synplicity’s industry-leading synthesis technology by adding graph-based physical synthesis and real-time simulator-like visibility into operating FPGA devices. The Synplify Prem.....
    Language : english Authorization: Retail Freshtime:2008-10-09 Size: 371MB
  • Synopsys Synplify FPGA 9.61 Linux

    Synplicity’s Synplify Premier Linux software is the ultimate FPGA timing closure and debug solution. It builds upon Synplicity’s industry-leading synthesis technology by adding graph-based physical synthesis and real-time simulator-like visibility into operating FPGA devices. The Synplif.....
    Language : english Authorization: Retail Freshtime:2008-10-09 Size: 478MB
  • Mentor Graphics AMS 2008.1 Win

    Mentor Graphics AMS 2008.1 (Mentor Graphics® 模拟/ 混合信号(AMS) 集成电路设计ADVance MS (AMS)包含有Mentor三种仿真内核,Eldo,ModelSim,和 Mach TA,支持数模混合电路各个不同阶段的仿真工作,从RTL,Gate-Level,到 transistor level。支持的语言包括有 VHDL, Verilog,VHDL-AMS,Verilog-A,SPICE 和 C。ADVance MS单一核心的解决.....
    Language : English Authorization: Retail Freshtime:2008-10-09 Size: 227MB
  • Cadence Encounter RTL Compiler 8.1

    Encounter RTL Compiler allows engineers to look across the entire design as they employ concurrent optimization techniques, such as making tradeoffs among timing, area, and powe To maximize performance, decrease die size, reduce power consumption, and boost productivity, designers need a global synt.....
    Language : english Authorization: Retail Freshtime:2008-09-24 Size: 450MB
  • Lattice ispLever 7.1 SP1

    attice Announces ispLEVER 7.1 Service Pack 1 FPGA Design Tool Suite Tool Suite Includes New 3rd Party Synthesis and Simulator Versions, Integrated ORCAstra Utility and Concurrent LatticeMico32 Release HILLSBORO, OR – SEPTEMBER 8, 2008 – Lattice Semiconductor Corporation (NASDAQ: LSCC) today anno.....
    Language : english Authorization: Retail Freshtime:2008-09-18 Size: 1.93G
  • Flomerics Flotherm 7.2

    Flomerics has released Version 7 of its Flotherm electronics thermal analysis software featuring a new Response Surface Optimization capability that Flomerics believes is unrivalled in computational fluid dynamics (CFD) analysis software. Earlier versions of Flotherm included a sequential optimizati.....
    Language : english Authorization: Retail Freshtime:2008-09-16 Size: 483MB
  • Ansoft Ephysics 3.0

    Ansoft Ephysics 3.0New in ePhysics v3: Enhanced coupling with HFSS and Maxwell based on automatic thermal and stress load mapping for multi-physics analysis. Resistive shell support to model thermal gap in transient analysis New scriptable reporter and ranged functions to extract maximum, .....
    Language : english Authorization: Pre Release Freshtime:2008-09-13 Size: 181MB
  • JMAG Designer 3.4

    JMAG is a simulation software for electromechanical design and development. Many companies and universities have supported and used JMAG since 1983. JMAG can accurately capture and quickly evaluate complex physical phenomena inside of machines. Users inexperience and experienced in simulation analy.....
    Language : english Authorization: Pre Release Freshtime:2008-09-12 Size: 474MB
  • Engineering Base 3.1.1.13

    Engineering Base..
    Language : english Authorization: Retail Freshtime:2008-09-10 Size: 816MB
  • Mentor Graphics FPGA Advantage 8.1

    FPGA Advantage is a complete Integrated Design Environment (IDE) targeting high-complexity FPGA device design. The FPGA Advantage IDE spans the RTL FPGA design flow featuring advanced design entry, verification, synthesis and implementation sub-flows. FPGA Advantage accelerates total product design .....
    Language : english Authorization: Retail Freshtime:2008-09-09 Size: 614MB
  • Mentor Graphics PADS 2007.3 with update2

    PADS®, Mentor Graphics’ world-leading desktop PCB design tool, enables you to develop PCBs within a highly productive, scalable, and easy-to-use environment. PADS solutions cover the spectrum of PCB development, from schematic entry to manufacturing preparation. But, unlike other products, we’re.....
    Language : english Authorization: Pre Release Freshtime:2008-09-09 Size: 565MB
  • Cadence Incisive Plan-to-Closure Methodology (IPCM) 6.0 Linux

    Cadence Incisive Plan-to-Closure Methodology将支持Open Verification Methodology,OVM,OVM基于Cadence的Incisive  Plan-to-Closure URM模块和Mentor的先进验证方法学模块。 ..
    Language : English Authorization: Retail Freshtime:2008-09-09 Size: 164MB
  • Cadence Incisive Enterprise Specman Elite Testbench (SPMN) 6.0 Linux

    Cadence® Incisive® Enterprise Specman Elite® Testbench uses executable specifications and designer-specified constraints to automate testbench generation, while simultaneously detecting misrepresentations of the specification. Its automated data and assertion checking speeds debug, while its fun.....
    Language : english Authorization: Retail Freshtime:2008-09-09 Size: 689MB
  • Cadence Incisive Formal Verifier (IFV) 5.8 Linux

    Cadence® Incisive® Formal Verifier allows design teams to start RTL block verification months earlier than when using traditional simulation-based techniques. Its formal, assertion-based approach and exhaustive analysis capabilities ensure verification quality by pinpointing the source of bugs and.....
    Language : english Authorization: Retail Freshtime:2008-09-09 Size: 734MB
  • Cadence Incisive Desktop Manager (EMGR20) 2.0 Linux

    Incisive Desktop Manager Automated verification managementIncisive Desktop Manager automates and guides the everyday deployment and visualization of verification tasks and results, increasing engineering productivity and reducing time to market.Cadence® Incisive® Desktop Manager accelera.....
    Language : english Authorization: Retail Freshtime:2008-09-09 Size: 397MB
  • Synopsys Liberty NCX 2008.06 sp2 Linux

    Synopsys Liberty NCX 2008.06 sp2 Linux-- The Fastest Path to Production Current-Source LibrariesSynopsys推出了其库编译器的升级版本,新增了对该公司复合电流源(CCS)模型的支持。该公司还推出了基于CCS的新型库特征化工具集Liberty NCX。Library Compiler接受开放源Liberty库格式,并将其编译到Synopsys工具的库内。.....
    Language : English Authorization: Retail Freshtime:2008-09-08 Size: 45MB
  • Synopsys CoreTools for IP Reuse Tools 2008.06.SP2

    在采用现有 IP核创建系统级芯片(SoC)时,关键是在设计周期之初,在目标环境中快速地配置和验证IP核。在采用多个IP模块和诸如AMBA的芯片级总线进行设计创建时,设计人员需要能够轻易地完成将多个IP模块连接到总线上并进行配置,从而能够将精力集中在设计中新的逻辑电路上。采用了DesignWare IP 重用工具,IP的创建者可以将自己的IP.....
    Language : English Authorization: Retail Freshtime:2008-09-08 Size: 44MB
  • Synopsys TetraMAX 2007.12 SP5 Linux

    TetraMAX® ATPG automatically generates high quality manufacturing test patterns. It's the only ATPG solution optimized for a wide range of test methodologies and integrated with Synopsys' patented DFTMAX™ compression the leading test synthesis tool. The unparalleled ease-of-use and high performanc.....
    Language : english Authorization: Retail Freshtime:2008-09-05 Size: 117MB
  • PCBM Matrix IPC-7351A LP Wizard 2009.18

    PCBM Matrix IPC-7351A LP Wizard 2009 是IPC7351标准的PCB封装(footpoint/cell)生成工具,用于生成符合DFM要求的PCB封装符号。::::::English Description::::::The IPC-7351A LP Wizard is a fantastic time saver. It is a land pattern calculator based on the IPC-7351A SMT land pattern standard that allows you to .....
    Language : English Authorization: Retail Freshtime:2008-09-05 Size: 0KB
  • IntuSoft ICAP4 IsSpice 8.1.6

    Pioneering PC based workstation simulation, Intusoft introduced its original IsSpice simulator in 1985. Now, several generations of simulation technology later, the 4th generation IsSpice4 simulator combines Berkeley SPICE 3 (Simulation Program with Integrated Circuit Emphasis) analog simulation wit.....
    Language : english Authorization: Retail Freshtime:2008-09-04 Size: 30MB
  • Ansoft HFSS 10.1 Linux

    The main HFSS interface is shown in Figure 1, which illustrates the main components of the gui. They are summarized as follows: • 3D Modeler Window This is the area where you create the model geometry. This window consists of the model view area (or grid) and the history tree as shown in Figure 2. .....
    Language : english Authorization: Retail Freshtime:2008-09-04 Size: 418MB
  • Cadence AMS Methodology Kit 5.1 Linux

    The Cadence® AMS Methodology Kit employs the Cadence Advanced Custom Design (ACD) methodology, which leverages silicon-accurate design methods to enable design teams to create differentiated silicon faster and with less risk. The kit delivers verified, packaged methodologies (demonstrated on a real.....
    Language : english Authorization: Retail Freshtime:2008-09-04 Size: 870MB
  • Cadence FINALE 6.1 Linux

    Cadence FINALE 6.1 Linux ..
    Language : english Authorization: Retail Freshtime:2008-09-04 Size: 544MB
  • Cadence Conformal Constraint Designer (ccd) v61.Linux

    Cadence Design System公司日前发布了一种新型形式分析工具,能生成、分析并验证设计师用于运行综合、时序分析和布局布线工具的设计约束(design constraints)的质量。 传统上,用户手动创建设计约束,采用事实上的Synopsys Design Constraint (SDC)标准格式,将它们输入到他们的工具内,运行工具,然后生成违反设计约束的清单。但Cad.....
    Language : English Authorization: Retail Freshtime:2008-09-04 Size: 545MB