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Mentor.Graphics.Calibre_2007

Mentor.Graphics.Calibre_2008

Size:

580M

Language: English
Protection: Flexlm
       Date: 2008.10.20
Software Type:  EDA
Platform:

  Windows

Release Type: License
Introduce   URL: http://www.mentor.com/products/ic_nanometer_design/news/

Mentor Graphics Corporation, (NASDAQ: MENT), the market and technology leader in high level synthesis solutions, today announced completion of the acquisition of the C synthesis assets of Agility Design Solutions Inc. These tools were formerly owned and marketed by Celoxica Holdings. Mentor Graphics intends to offer continued sales and support to existing customers, as well as an upgrade path to Catapult C® Synthesis, the market-leading high level synthesis tool.

The electronic system level (ESL) products associated with this acquisition are the Handel C-based algorithm synthesis flow found in the DK Design Suite, PixelStreams and the RC Series of FPGA development and prototyping boards. Key employees will join Mentor to ensure continued product support.

“This agreement reaffirms Mentor’s leadership in ESL design with the richest ESL tool suite on the market,” said Simon Bloch, vice president and general manager of Mentor’s Design Creation and Synthesis Division. “Mentor is happy to work with Agility to provide its customers a home that gives them full support for their legacy products until they are ready to upgrade to Catapult® C Synthesis on their own terms and schedule.”

“Mentor understands ESL very well and is offering our customers continued support and a way forward with a technology that has proven itself to be a time-to-market saver,” said Dave Burow, Agility’s CEO. “By working with Mentor Graphics, we can safeguard the trust that our customers put in us.”

Enabling Accurate Post-layout Functional Verification:
The New Nanometer Silicon Model
Shrinking geometries and increasing design size in the nanometer era have enabled greater functionality on a single chip. But with the increased functionality comes new complexities that create more problems in the attempt to attain design closure. This requires an electrical representation of the chip that accounts for the actual physical design of its devices and interconnect, and accurate silicon model. Calibre xRC and Calibre xL meet the demands of nanometer designs with a comprehensive approach to device and parasitic extraction to compose accurate silicon models enabling a large variety of post-layout analyses.

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