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Softname: |
Actel.Designer.v8.3 | ||
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Update link |
Information | ||
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Size: |
2DVD |
2 |
| Language: | English | ||
| Protection: | FlexLM | ||
| Date: | 2008.04.01 | ||
| Software Type: | EDA Until | ||
| Platform: |
Windows,Linux |
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| Release Type: | License | ||
| Introduce | URL: | www.actel.com | |
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Designer is Actel's powerful physical implementation software tool suite for all Actel FPGAs. After completing design entry and functional verification using Libero IDE tools or your favorite front-end design tools, simply import the resulting netlist into Designer to set timing constraints and performing place-and-route, timing analysis, power analysis, and program file generation. Designer provides full power optimization and analysis tools for Actel's low-power flash FPGA families, including IGLOO and ProASIC3L, the latest addition to the ProASIC3 family. IGLOO, IGLOO PLUS, and ProASIC3L LVCMOS 1.2 v I/Os1.2 volt LVCMOS I/O technology is the lowest VCCI standard available and is now available for ProASIC3L, 1.2 volt IGLOO, and 1.2 volt IGLOO PLUS devices. LVCMOS 1.2 is the default I/O selection for these devices. To further ensure low-power operation, the drive strength is set at 2 mA for all devices with the exception of the IGLOO AGL030V2 and AGL015V2 where the drive strength is set to 1 mA. Use of 1.2 volt I/O allows operation of IGLOO, IGLOO PLUS, and ProASIC3L devices, both Core and I/Os, from a single 1.2 volt power supply. 1.5 volts is still required for programming. IGLOO and ProASIC3L PLL/CCC UpdateExisting IGLOO, IGLOOe, and ProASIC3L designs that have a PLL/CCC core may have an invalid configuration. When you open your design with v8.3, a check will be run and a message will instruct you to regenerate the programming file if necessary. SmartPower New FeaturesYou can now enter your own temperature and voltage values to device modes, such as Active, Standby, Flash*Freeze. This allows you to create additional "what-if" scenarios or profiles to test your design under various operating conditions. This feature is available for IGLOO, IGLOO PLUS, ProASIC3L, ProASIC3, and Axcelerator. Automatic glitch filtering during the VCD read process removes spurious transitions based on the minimum pulse width for the target device, providing a more accurate analysis of power. You can now extract "Probabilities" from VCD files. In addition to extracting the average frequency of pins from a VCD file, SmartPower will now automatically compute the "probabilities" (or likelihood) of enable signals being active. The probabilities, expressed in percent, are used with the enable rates feature to provide greater accuracy for RAM/FIFOs and tri-stated IOs. Repair of Minimum Delay ViolationsThe Advanced Layout Option to repair minimum delay violations for Fusion, ProASIC3E, and IGLOOe devices has been enhanced to take advantage of programmable delays on I/O Input buffers. The feature inserts delay in paths where the minimum delay in not being met, while simultaneously checking maximum delays to ensure no violations are being introduced.
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| download link | |||
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http://www.caxsoft.net/
http://softworld.tux.nu |
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