电路板设计解决方案市场和技术领导者Mentor Graphics宣布推出HyperLynx 7.7版，这套强大而易于使用的布局前和布局后讯号完整性仿真与分析工具包含多项生产力和技术增强功能，最适合支持PCI-Express、Hyper Transport、XAUI和SATA/SAS等最新的SERDES联机标准。　这是专门用于Mentor Graphics Vendor-Independent Flow 2006-IND2006的版本。　 　　
「 高速数字设计实用手册」(High-Speed Digital Design: A Handbook of Black Magic) 一书作者Howard Johnson博士表示：「HyperLynx 7.7新增加任意线路图编辑器和先进的高速分析功能，不但产品变得更实用，操作也更简单。所有数字设计人员都应该购买、学习和使用这套工具。」　　 　
　　新提供的生产力增强功能包括简单易用的「任意形状」(free-form) 传输线路编辑器，设计人员可于布局前利用它尝试各种设计 (what-if) 和发展设计约束条件，进而轻松地建立所需的SPICE和S参数模型。HyperLynx 7.7会将所有讯号损耗来源列入考虑，包括封装寄生参数、连接头和导孔损耗以及电路板的电阻性损耗和介质损耗。HyperLynx 7.7会透过一套易于使用的环境管理这些讯号完整性效应，这使其成为全世界应用最广泛的讯号完整性软件。HyperLynx 7.7版还采用Mentor Graphics独有的「导孔显示」(Via Visualizer) 技术，这对于电路板导孔的深入分析有很大帮助。其它技术增强部份还包括批次仿真、更简单的使用者界面、更多的SERDES眼形罩幕 (eye mask)、更强大的SPICE建模功能以及超过13,000种新增IBIS模型。这些增强功能都兼容于所有主要的电路板布局环境，硬件工程师可以更有效地分析10亿位等级 (multi-gigabit) 串行式电路板联机。　　 　　 　
SERDES (SERialization/DE-Serialization) 　　
　 SERDES是一种快速窜红的连结技术，它能利用速率高达每秒数千兆位的串行驱动器和接收器将半导体组件和FPGA连接在一起。SERDES讯号是透过差动对传输资料，而非采用传统的宽总线架构，零件之间的资料速率最高达10 Gbps。除了资料产出大幅提升之外，SERDES还能减少电路板绕线面积、电路板厚度以及零件和连接头的接脚数。　　 　　
　「对许多工程师和电路布局设计人员而言，印刷电路板的SERDES联机设计与分析是一种全新概念。」Mentor Graphics副总裁暨系统设计部门总经理Henry Potts表示，「新推出的HyperLynx不但简化设计作业，还提供完整的布局前和布局后分析能力，现在将有更多使用者可以利用这种联机技术发展效能更高的系统。」　　 　
　　主要FPGA厂商的评论　　
　「视讯和影像处理等应用都已采用PCI-Express等高速串行联机技术。」Altera的EDA厂商公关主管James Smith表示，「HyperLynx 7.7提供多种更强大功能，只要搭配Altera的Stratix GX设计套件就能使客户确信其系统的高速SERDES线路能够正常运作。」　　 　　
　「Xilinx致力为客户提供先进的连结解决方案，HyperLynx 7.7新功能使客户更容易导入我们的10Gbps RocketIO™技术。」Xilinx策略公关资深经理Jasbinder Bhoot表示，「我们与Mentor Graphics的合作很密切，这使双方共同客户得以充份利用该技术的优点。」　　 　
　　设计套件　　　
为进一步推广SERDES和其它新出现的联机标准，Mentor Graphics持续与主要的半导体组件和FPGA供货商合作，共同提供更多种技术 (USB、PCI-X、DDR) 和特定半导体组件 (例如Xilinx RocketIO和Altera Stratix GX) 专用的设计套件。这些套件包含模型、参考设计和设计说明，它们让工程师能够立即以新技术展开设计工作。　　 　　
　支持所有主要的电路板布局工具　　
　 HyperLynx兼容于Mentor所有电路板设计流程，包括Board Station® Series、Expedition™ Series以及PADS电路板设计环境，另外它也兼容于Cadence、Altium和Zuken的电路板布局系统。　　 　　
　价格与供应时程　　 　
Mentor Graphics已开始供应HyperLynx 7.7版，入门版售价从4,133美元起，全功能版售价则为39,200美元。Mentor Graphics还另外提供单机使用授权 (node locked) 以及浮动授权 (floating license)。

::::::English Description::::::

Mentor Graphics® Corporation (Nasdaq: MENT), the market and technology leader in printed circuit board (PCB) design solutions, today announced the immediate availability of HyperLynx® 7.7, the latest version of its powerful and easy-to-use tool suite for pre- and post-layout signal integrity (SI) simulation and analysis. HyperLynx 7.7 includes significant productivity and technology enhancements targeted at classic high-speed bus technologies, as well as the rapidly emerging SERDES (SERialization/DE-Serialization) interconnect standards for connecting serial drivers and receivers.

“I use HyperLynx because it is one of the few accurate circuit simulators with coupled lossy-line models and an integrated 2D field solver,” said Dr. Eric Bogatin, industry expert and author of Signal Integrity Simplified. “Plus, it is far and away the quickest tool on the market to learn with a five minute learning curve. With the release of HyperLynx 7.7, its value for high-speed serial link analysis has more than doubled.”

“Gigabit SERDES interconnects are the industry’s answer for faster data transfer,” said Henry Potts, vice president and general manager of Mentor Graphics Systems Design Division. “At current multi-gigabit rates, the ability to simulate is a necessity. HyperLynx 7.7 is a further example of Mentor’s commitment to technology leadership. The release of HyperLynx 7.7 is specifically targeted at increasing design productivity and efficiency for SERDES simulation.”

HyperLynx 7.7 Enhancements
HyperLynx 7.7 provides several industry-leading enhancements, including:

• The integration of Mentor’s mixed-signal simulation engine, enabling simultaneous simulation of AMS, Eldo® (SPICE), IBIS IC models, SPICE package models and frequency-dependent S-parameter models in the same channel
• A Touchstone model viewer, enabling engineers to examine S-parameter models and to quickly check for causality and passivity violations-common problems with these models
• Mentor’s industry-leading complex-pole fitting algorithms which allow large S-parameter files to be compiled natively for Mentor simulators producing an order of magnitude increase in simulation speed
• A pre-layout tool offering complete padstack editing, giving the engineer the ability to compare through-hole, blind or buried vias during channel analysis before going to layout
• A new “fast eye diagram” capability for SERDES design that incorporates Bit Error Rate (BER) prediction and bathtub curves, saving time by enabling engineers to examine eye quality across millions or even billions of cycles in just a matter of minutes
• The unique ability to predict the worst-case bit stimulus sequence that would produce a maximally closed eye diagram

Productivity enhancements include:

• Significant oscilloscope improvements and an extensive upgrade to the batch simulation utility
• The ability to view current waveforms, import/export functionality with Mentor’s Waveform Analyzer and EZWave™ waveform viewers, and ten automated scope measurements that include flight-time, eye width and height and DDR2 de-rating
• Post-layout batch simulation with user-requested features, such as reusable electrical rule sets, wildcard searches for groups of nets, sorting of nets by driver edge rate and batch auditor