::::::English Description::::::Built on an advanced software architecture, the unique core technology in the AWR Design Environment is a modern object-oriented data model that is inherently open and flexible compared to legacy design tools. The AWR Design Environment elevates the product development.....
Language : english Authorization: Retail Freshtime:2008-08-05 Size: 126MB
Green Hills的MULTI集成环境综合了软件开发和调试过程中要用到的各种工具,它由编译器、交叉工具包、集成开发环境和调试接口等组成.这是能够支持Motorola系列的68K、ColdFire的工具包.::::::English Description::::::Green Hills Software provides complete solutions for the development of embedded and real-time a.....
Language : English Authorization: Pre Release Freshtime:2008-08-02 Size: 168MB
::::::English Description::::::IAR Embedded Workbench for M16C provides full support for devices in M16C/1x, M16C/6x and R8C series and generates very compact and efficient code. Built-in plugins to different hardware debug systems and RTOSes are included in the standard edition.Highlights in versio.....
Language : english Authorization: Retail Freshtime:2008-07-23 Size: 86MB
::::::English Description::::::IAR Embedded Workbench for M32C provides full support for devices in M32 C and M16C/8x series and generates very compact and efficient code. Built-in plugins to various hardware debug systems and RTOSes are included in the standard edition. Highlights in version 3.21S.....
Language : english Authorization: Retail Freshtime:2008-07-23 Size: 58MB
CodeVisionAVR,是一款轻量级的AVR单片机开发工具。::::::English Description::::::High Performance ANSI C Compiler, Integrated Development Environment, Automatic Program Generator and In-System Programmer for the Atmel AVR family of microcontrollers. ..
Language : English Authorization: Retail Freshtime:2008-07-21 Size: 36MB
IAR Embedded Workbench for National CR16C 2.12A.::::::English Description::::::IAR Embedded Workbench provides extensive support for all devices in CR16C family and generates very compact and efficient code. Debug interface to Nexus class I is included in standard edition and SC14 co-processor su.....
Language : english Authorization: Retail Freshtime:2008-07-21 Size: 45MB
::::::English Description::::::ELECTRA™ is a new generation of Shape-Based Autorouting software for PC boards. ELECTRA is a new generation of Shape-Based Autorouting software for PC boards. By contrast with traditional gridded maze autorouters, a shape-based approach allows for more efficient .....
Language : english Authorization: Pre Release Freshtime:2008-07-21 Size: 6MB
PCB Matrix PCB Libraries LP (Provisional)7.01.07是IPC7351标准的PCB封装(footpoint/cell)生成工具,用于生成符合DFM要求的PCB封装符号。::::::English Description::::::The IPC-7351A LP Librarian is a fantastic time saver. It is a land pattern calculator based on the IPC-7351A SMT land pattern standard that al.....
Language : English Authorization: Pre Release Freshtime:2008-07-14 Size: 21MB
::::::English Description::::::Impulse C allows you to compile C-language directly into optimized logic ready for use with popular FPGA devices. Use the Impulse tools to quickly prototype mixed software/hardware systems and perform design iterations in ust minutes or hours, instead of days or weeks......
Language : english Authorization: Retail Freshtime:2008-07-05 Size: 171MB
::::::English Description::::::EASE offers the best of both worlds with your choice of graphical or text based HDL entry. You don not need to be a master of either Verilog or VHDL. When you are creating a new design, just enter your design using your mix of graphics and text. EASE automaticall.....
Language : english Authorization: Retail Freshtime:2008-06-29 Size: 28MB
Altera为FPGA、CPLD和结构化ASIC器件提供Quartus® II 设计软件。Quartus® II 设计软件提供了一套最先进的工具,用于系统级设计、嵌入式软件编程、FPGA和CPLD设计、综合、布局布线、验证以及器件编程。Quartus II软件支持所有Altera的最新器件系列。SOPC Builder是一个自动系统开发工具,它极大地简化了创建高性能可.....
Language : English Authorization: Pre Release Freshtime:2008-06-16 Size: 2.78G
Additional Enhancements to Quartus II Software Version 8.0
* New tasks window: Provides an interactive design flow console that guides users through the FPGA design flow.SOPC Builder: Offers support for incremental compilation and adds key intellectual property (IP) blocks to its design library.....
Language : english Authorization: Retail Freshtime:2008-06-09 Size: 2.06G
::::::English Description::::::Digital signal processing (DSP) system design in Altera® programmable logic devices (PLDs) requires both high-level algorithm and HDL development tools. Altera s DSP Builder integrates these tools by combining the algorithm development, simulation, and verification.....
Language : english Authorization: Retail Freshtime:2008-06-09 Size: 106MB
::::::English Description::::::Novas Design Comprehension Solutions Novas orchestrates a collection of leading-edge solutions that ease design comprehension throughout the verification flow, from systems to silicon. Our debug systems reduce the time it takes to understand complex logic, giving you .....
Language : english Authorization: Pre Release Freshtime:2008-05-30 Size: 679MB
nLint is a comprehensive HDL design rule checker fully integrated with the Verdi and Debussy debug systems. The Debussy system accelerates users understanding of complex designs to improve design, verification, and debug productivity. nLint adds the ability to fully analyze the HDL for syntax and se.....
Language : english Authorization: Pre Release Freshtime:2008-05-30 Size: 128MB
::::::English Description:::::: HDL Companion is the HDL designer Swiss army knife. It will help you to get and keep a good overview of any HDL design, including third party IP, legacy code and other HDL sources. Complete design directories and design files are dragged and dropped into HD.....
Language : english Authorization: Retail Freshtime:2008-05-25 Size: 15MB
一款安装简便,使用简单,整合极佳的软件开发测试环境工具。(IDDE).通过一个简单直观的界面来对你的项目进行全面的管理。具有直观的C/C++编码器,先进的图形模拟工具,以及VisualDSP++ Kernel (VDK)等等功能。::::::English Description:::::: VisualDSP++ 5.0 is an easy-to-install and easy-to-use integrated software devel.....
Language : English Authorization: Pre Release Freshtime:2008-05-24 Size: 221MB
::::::English Description::::::While today’s chip designs demand increasing speed and performance, designers are also faced with the challenge of verifying their chips at both analog and logic levels expediently due to shortened product life cycle. Full-chip simulations require prudent setup a.....
Language : english Authorization: Retail Freshtime:2008-05-24 Size: 10MB